MOS devices, including laterally diffused MOS (LDMOS) devices, are employed in a variety of applications, such as, for example, power amplifiers in wireless communications systems. With regard to the direct current (DC) performance of LDMOS devices, it is generally desirable to have a low on-state resistance and a high transconductance. The on-state resistance of a low-voltage (e.g., breakdown voltage of less than about 10 volts) LDMOS device is dominated primarily by a resistance in a channel region of the device. For instance, in a low-voltage LDMOS device, the channel resistance accounts for about eighty percent of the total on-state resistance of the device. In comparison, the on-state resistance of a high-voltage power MOS field-effect transistor (MOSFET) device is dominated primarily by a resistance of a drift region in the device.
To achieve a low on-state resistance and/or higher power handling capability, a wider channel is typically required. However, forming a device having a wider channel will consume more chip area due to the planar nature of the device. Moreover, an output capacitance of the device, which is a function of a perimeter of a P-N junction in the device, will increase accordingly as a function of the channel width. The increase in output capacitance of the device undesirably affects high-frequency performance of the LDMOS device (e.g., above about 1 gigahertz (GHz)).
It is known to increase the channel width of an LDMOS without necessarily consuming significant additional chip area by employing a folded gate LDMOS structure, as described in a paper by Yuanzheng Zhu et al., entitled “Folded Gate LDMOS Transistor with Low On-Resistance and High Transconductance,” IEEE Transactions on Electron Devices, Vol. 48, No. 12, December 2001, which is incorporated by reference herein. However, while the folded gate configuration of the LDMOS device may produce a device having reduced on-state resistance without significantly increasing chip area, this methodology provides essentially no benefit in improving high-frequency performance since the perimeter of the P-N junction in the device, and thus junction capacitance, remains the same as if the channel region were formed substantially planar.
There exists a need, therefore, for an MOS device capable of improved high-frequency performance and on-state characteristics that does not suffer from one or more of the above-noted deficiencies typically affecting conventional MOS devices. Furthermore, it would be desirable if such an MOS device was fully compatible with standard integrated circuit (IC) process technology.